Double-gate dielectric stacks for NVSM (flash) memories

It is commonly perceptible that flash memories based on NAND and NOR logic gates are experiencing tremendous growth because of new and more demanding applications in, particular, low power solid-state storage and mobile devices. The key technologies for nowadays Non-Volatile Semiconductor Memories (NVSMs), i.e. floating gate (FG) and silicon-oxide-nitride-oxide-silicon (SONOS), are already running into the fundamental barriers. Novel gate structures exploiting charge trapping layers based on high relative permittivity (high-k) materials are believed to overcome scaling issues.

Part of my wrok are fesibility studies of double-gate dielectric stcks for memory devices. Below, is the example of work which is focused on gate dielectric structures for NVSM devices which consist, in contrary to commonly found in the literature, only two gate dielectric layers. In our recent work, we have demonstrated the feasibility of application such double-gate dielectric stacks in flash memories for the first time. The gate structures for NVSMs are based of pedestal (bottom) silicon oxynitride (SiOxNy) layer obtained by Plasma Enhanced Chemical Vapor Deposition (PECVD) process and Atomic Layer Deposited (ALD) hafnium oxide (HfO2) or aluminum oxide (Al2O3), as the top dielectric layer. It's an example of research towards developing and characterization of MOS stacks for NVSM applications

Presented results have proved that investigated in the course of this work double-gate dielectric stacks are promising candidates for application in NVSM devices, however, further characterization of MISFETs is necessary.

© 2016 by Robert Mroczyński.

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