Electro-physical properties of gate-last MOSFETs with low-temperature SiOxNy/HfOx stack

December 19, 2017

The aggressive scaling of modern MOS (Metal-Oxide-Semiconductor) structures have brought the thickness of gate dielectric layers into a fundamental limit, and thus, the introduction of high-k dielectric materials into a gate-stack. As a consequence, several problems of semiconductor/dielectric interface have drawn the attention of engineers, such as time-dependent dielectric breakdown (TDDB), or interface-states generation, and enhanced charge-trapping. The incorporation of fluorine ions at the semiconductor sub-surface region has been investigated as a technology to improve the electro-physical properties of a MOS structure interface. A number of methods of fluorine incorporation into the silicon substrates has been proposed, among them: classical ion implantation followed by a high temperature drive-in, or rapid thermal processing (RTP) in O2 with diluted NF3. In this work, we demonstrate the feasibility of introduction of fluorine ions from RF plasma, that is performed in a standard Reactive Ion Etching (RIE) reactor at room temperature (RT). The implantation process was adopted to the MOS Field-Effect Transistors (MOSFETs) technology with gate-last low-temperature SiOxNy/HfOx double-gate dielectric layers. The decrease of the interface state density (Nit), and effective charge (Qeff) were demonstrated what results in the enhancement of mobility (µeff), and lowering threshold voltage (Ut) value of investigated MOSFETs.

 

 

 

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© 2016 by Robert Mroczyński.

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